Time: 2025.11.08
In September of this year, TSMC confirmed the closure of its 6-inch fab 2 in the Hsinchu Science Park and the consolidation of capacity at its 8-inch fabs 3, 5, and 8 in Hsinchu, with approximately 30% of its employees being relocated to advanced process technology plants in southern Taiwan. This portion of the 6-inch capacity primarily served low-end chips for automotive and consumer electronics. Affected by fluctuations in global automotive chip demand, its capacity utilization rate had been consistently below 70% in recent years, and equipment depreciation was nearing its end. Closure will save approximately 12% in per-fab operating costs.
Simultaneously, TSMC announced its exit from the gallium nitride (GaN) foundry business within two years. This business belongs to the mature process technology extension field, but TSMC's global GaN foundry market share is less than 5%, and it faces fierce competition from Win Semiconductors and Infineon. In 2024, related revenue will only account for 0.8% of total revenue.
Affected by the US revocation of its "Verified End User" (VEU) license at its Nanjing plant, TSMC's Nanjing plant is facing equipment supply difficulties for its 16nm and 28nm capacity. However, TSMC emphasized that it is "communicating with the US" and will continue operations in the short term.
Data from 2025 shows that 7nm and below advanced processes will contribute 63% of TSMC's revenue, with 3nm process capacity utilization reaching 100%. Even before mass production, 2nm has secured orders from core customers such as Apple and Qualcomm, and the number of design projects is expected to exceed the combined number of 3nm and 5nm projects within four years of mass production. In contrast, mature processes have a gross margin of less than 30%, naturally becoming a priority for resource allocation reduction.
TSMC's contraction has created opportunities for its competitors. Currently, UMC and SMIC have specifically expanded their 28nm and 40nm capacity. In 2025, UMC's revenue from mature processes increased by 18% year-on-year, mainly from its former automotive chip customers. SMIC, leveraging demand from the Chinese automotive electronics market, has increased its 14nm/28nm capacity utilization rate to 85%.
2nm Mass Production Imminent, 1.4nm R&D Accelerated
While structurally contracting its mature processes, TSMC has established a technological hierarchy at 7nm and below nodes: "3nm mass production, 2nm pilot production launch, and 1.4nm R&D breakthrough." Coupled with the expansion of advanced packaging capacity, it continues to lead the global semiconductor manufacturing race.
According to TSMC President C.C. Wei's public statement in October 2025, the 2nm process has successfully entered the pilot production stage, with yield performance "meeting expectations," and rapid mass production is planned for 2026. This process continues the FinFET architecture improvement route, introducing more advanced multi-exposure technology to achieve a performance breakthrough compared to the 3nm process, reducing chip area by 5% and improving energy efficiency by 15%.
In terms of production capacity, the Hsinchu Baoshan Fab 20 and Kaohsiung Fab 22 have completed equipment installation and commissioning, and by the end of 2025, monthly production capacity will increase to 50,000 wafers, with a single wafer price reaching US$30,000, setting an industry record. On the customer side, Apple alone accounts for nearly half of the capacity, which will be used for the A20 chip in the 2026 iPhone 18 series; Qualcomm, AMD, MediaTek, Intel, and other companies have also secured capacity quotas, forming a diversified demand matrix covering consumer electronics and high-performance computing (HPC).
As the current mainstream advanced process, 3nm accounted for 23% of revenue in the third quarter of 2025, and capacity utilization remained at 100% saturation. In addition to traditional high-end mobile SoCs, next-generation AI accelerators such as NVIDIA's GB200 have partially adopted the 3nm process, achieving dual optimization of computing power and energy efficiency through high-density transistor integration. To meet surging demand, TSMC plans to increase its 3nm monthly capacity from the current 120,000 wafers to 150,000 wafers by 2026, and simultaneously launch the N3E (enhanced) process, further reducing power consumption by 10%, primarily targeting data center customers.
Meanwhile, TSMC has initiated intensive research and development on its 1.4nm process, expecting to achieve mass production between 2027 and 2028. This process will likely employ a completely new transistor architecture, reducing chip area by another 5% compared to 2nm, but faces challenges from a surge in equipment investment and process complexity—the procurement cost of a single High-NA EUV lithography machine has exceeded $350 million, and total R&D investment is expected to exceed $5 billion.
Industry analysts predict that TSMC will raise chip prices for processes below 5nm starting in January 2026. TrendForce sources say the company notified its major customers last September. Average prices will rise by 3% to 4%, but reports from Taiwan indicate that the price increase for the most advanced process nodes could be as high as 10%.
Furthermore, starting in January 2026, the price of the 2nm process node will increase for four consecutive years. By 2030, the cumulative increase in the price of the most advanced process nodes could reach double digits, which will affect the cost of cutting-edge chips used in artificial intelligence, high-performance computing, and other demanding applications.
